A methodology was developed for the hardware implementation of an optimization-based control algorithm. A combination of simulations and emulations is used in series of parametric tests to determine parameters of the design. The proposed hardware architecture encompasses a general purpose microprocessor, an iterative matrix coprocessor, and a Logarithmic Number System that gives advantages in terms of size and power consumption in small word lengths. The developed control chip is suitable for constrained applications characterized by fast sampling time and small size.
A U.S. Utility patent application has been filed